The present invention relates to a method for the manufacture of an active matrix display screen, based on thin-film transistors (TFT) and capacitors).It is used more particulary in the construction of liquid crystal display circuits.
TFT circuits are mainly used in the manufacture of active matrix display screens. In this type of screen, an electronic memory formed from memory points distributed over the entire surface of the screen, stores the video signal throughout the duration of the picture. The electrooptical transducer (e.g. a liquid crystal) is in contact with each memory point and is excited throughout the duration of a picture whereas in system without an electronic memory, the transducer is only excited for the duration of one row. The optical effect and the permitted multiplexing level are consequently much greater.
The TFT makes it possible to produce such an electronic memory on a glass substrate. Each memory point is located at the intersection of a connection column and a row and is constituted by a transistor and a capacitor. In the case where the transducer is a liquid crystal, the plates of the capacitor can be constituted by the electrodes of the actual liquid crystal cell. Thus, the memory point amounts to a TFT and a capacitor, whereof one of the plates is constituted by the electrode arranged on the wall of the cell containing the TFT, the other plate being formed by the counter-electrode arranged on the other wall of the cell.
Such a structure is shown in FIG. 1, where it is possible to see on the one hand a lower wall 10 carrying the conductive columns 12 and conductive rows 14, a TFT 20 and a transparent electrode 22, and on the other hand an upper wall 24 covered by an also transparent counter-electrode 26.
Besides active matrixes, other circuits can be produced with TFT's and, e.g., all or part of shift registers. Such circuits can be used in the low speed vertical register permitting the row-by-row switching of the display screen.
Methods for the manufacture of circuits based on TFT's and capacitors are already known. FIG. 2 (a, b) illustrates a procedure described by A. J. SNELL et al. in an article entitled "Application of amorphous silicon field effect transistors in addressable liquid crystal display panels" published in "Applied Physics", 24, pp. 357-362, 1981. The TFT is formed by a chromium grid G deposited on an insulating substrate 30, a silicon nitride (Si.sub.3 N.sub.4) insulating layer 32, an amorphous silicon layer 34 (aSi), an aluminium source S and a drain D. The lower capacitor plate is formed from an indium - tin oxide layer 38. The connection between the TFT and the plate is by a drain D extended by a tab 40 following a contact hole 42 made in insulating layer 32. The complete circuit is constituted by a plurality of such structures arranged in matrix form. The grids G are constituted by connection rows 44 and the sources by columns 46.
The process for producing such a structure involves five masking levels:
the first for etching the conductive layer 38, PA1 the second for etching grids G and etching rows 44, PA1 the third for opening the windows 42 in insulant 32, PA1 the fourth for etching semiconductor 34, and PA1 the fifth for etching the source - drain contacts. PA1 the first for etching the transparent electrode 66, PA1 the second for etching the aSi layer 52, the third for etching the S contacts 54 and 56, PA1 the fourth for opening windows 60, 62 in insulant 58, PA1 the fifth for etching the drain and source metal coatings, and PA1 the sixth for etching the grid metal coatings. PA1 deposition of an insulating substrate of a first transparent, conductive material, PA1 first photogravure aplied to the first layer to form blocks forming one of the two plates of the future capacitors, PA1 as well as sources and drains for the future transistors, PA1 deposition of a hydrogenated, amorphous silicon layer, PA1 deposition of an insulating layer, deposition of a layer of a second conductive material, and PA1 second photogravure applied to the silicon layer - insulating layer - conductive layer assembly in order to define control grids for the transistors.
Such a process suffers from two disadvantages. Firstly a number of masking operations are required. It then necessitates the etching of the sources and the drains being selective and non-polluting with respect to the amorphous silicon, which must be protected by an adequate passivation, which must not produce an accumulation zone on the upper interface.
Another procedure for producing TFT's is known, in which unlike in the first-mentioned process, the TFT has its source and drain contacts in the lower part and its grid in the upper part. This procedure is described by M. MATSUMURA et al. in the article entitled "Amorphous silicon integrated circuit, published in "Proceedings of the IEE", vol. 68, No. 10, October 1980, pp. 1349-1350 and is illustrated by FIG. 3. On to a glass support 50 is deposited an amorphous silicon layer 52, followed by a n.sup.+ doped silicon layer, which is then etched to form the source contact 54 and drain contact 56. An insulating silica layer 58 is deposited on the entity. Openings 60, 62 are formed in the insulating layer to give access to the source and drain, whilst an aluminium layer forms the grid 64. The capacitor plate is formed by a transparent, conductive oxide layer 66, covered with a silica layer 58. An opening 68 is made in said layer and a connection 70 connects source 54 to electrode 66.
Such a structure requires the following six masking levels:
Thus, such a procedure is very complex.